1. Field of the Invention
The invention relates generally to semiconductor memories, and more particularly, to a semiconductor memory applied for changing sequence of data in accordance with a predetermined rule. The invention has particular applicability to microprocessors for executing Fast Fourier Transform (FFT) or an arrangement conversion in picture processing.
2. Description of the Background Art
In general, in data processing, a change of the sequence of a plurality of data is often required. For example, in order to effect data processing for Fast Fourier Transform (hereinafter referred to as FFT), the sequence of a plurality of data is changed. In this case, once the plurality of data are stored in a data array, the data stored are supplied from the data array in accordance with a sequence required in FFT. A detailed description as to the operation for FFT may be found, for example, in a text entitled "THE FAST FOURIER TRANSFORM" by E. ORAN BRIGHAM (Drentice-Hall Inc.).
When an operation is carried out for FFT by a microprocessor, the operation for FFT is executed in accordance with a program stored in a memory of the microprocessor. That is, the CPU carries out the process for changing the sequence of data required in FFT in accordance with a stored program. This causes increase of the amount of the operation to be processed by the CPU. Accordingly, the time required for the operation process by the CPU is increased. Particularly, in the operation process for FFT, a change of the sequence of the data to be processed is often required, so that the burden of the CPU is increased.
In addition to the conversion of the data sequence for the above-mentioned FFT, the conversion of the data sequence as well is often required in the field of image processing. For example, in an arrangement conversion in image processing, that is, in the case where an image is turned 90.degree., the conversion of the data sequence is required. In general, in image processing, high-speed data processing is required, so that the amount of the operation of the CPU should also be decreased in this case. Accordingly, a decrease in the amount of the operation of the CPU contributes to the high-speed data processing.
FIG. 8 is a block diagram of a conventional static random access memory (hereinafter referred to as SRAM) provided in a microprocessor Referring to FIG. 8, this SRAM 95 comprises a memory cell array 1 including memory cells disposed in m rows and n columns (not shown), a decoder 8 for designating a memory cell row, an input circuit 5 for writing input data (parallel data having n bits) DI supplied to the designated memory cell row, and an output circuit 6 for reading the stored data from the designated memory cell row. One data which may be written in the memory cell array 1 includes n bits (for example, 8, 16, 32 bits and so on). A total of m data may be stored in this memory cell array 1. That is, this memory cell array 1 has a storage capacity of n bits.times.m words. In order to make the description simple, a description will be made as to a case of m=16 in the following.
In write operation, the decoder 8 receives an address signal AD generated from an address generation circuit in the microprocessor. The decoder 8 designates one of 16 memory cell rows M0 to M15 in response to the address signal AD. The input circuit 5 receives the input data DI generated from the arithmetic unit in the microprocessor. The input circuit 5 drives a bit line (not shown) in response to a write enable signal WE generated from the controller in the microprocessor. That is, the bit line is driven based on the input data DI applied. As a result, the input data DI is written in the designated memory cell row.
In read operation, after the decoder 8 designates a memory cell row, the output circuit 6 including a sense amplifier (not shown) is activated in response to a sense enable signal SE. The signal SE is generated from the controller in the microprocessor. Accordingly, the data stored in the designated memory cell row is amplified by the output circuit 6, and the amplified signal is generated as output data (parallel data having 8 bits) DO. The output data DO is sent to the arithmetic unit.
FIG. 9 shows an example of a circuit diagram of the input circuit 5, the output circuit 6, and one memory cell row shown in FIG. 8. Referring to FIG. 9, the input circuit 5 includes bit line activating circuits 51 to 5n for driving respectively n pairs of bit lines BL, BL. Each bit line activating circuit 5l to 5n drives a bit line pair BL, BL simultaneously in response to the write enable signal WE. One memory cell row provided in the memory cell array 1 includes n SRAM memory cells MCl to MCn connected to word lines WL. The word lines WL are connected to the decoder 8 shown in FIG. 8. The output circuit 6 includes n sense amplifiers 61 to 6n respectively connected to each bit line pair BL, BL. Each sense amplifier 61 to 6n is activated simultaneously in response to the sense enable signal SE.
FIG. 10 shows another example of a conventional SRAM provided within a microprocessor. While SRAM 95 shown in FIG. 8 included decoder 8 for selecting a row only, SRAM 96 shown in FIG. 10 includes a column decoder (C.D.) 8b for column selection in addition to a row decoder 8a for row selection. Column decoder 8b generates a column select signal for controlling a selector circuit 9a in response to a column address signal supplied from an address generation circuit. Selector circuit 9a selects a column to be accessed in response to the applied column select signal.
When the SRAM shown in FIG. 8 is used for changing the above-mentioned data sequence, it is impossible to avoid the increase in the amount of the operation to be processed by the CPU. That is, in order to effect a changing process of data sequence, it is necessary to make different the sequence for designation of a memory cell row in which data is to be written and the sequence for designation of a memory cell row from which data is to be read, in accordance with a predetermined rule. For example, in order to carry out bit reverse addressing for FFT, at first, a write address signal is generated from the address generation circuit, and the input data DI is written in the memory cell row designated by-the write address signal. A read address signal is then generated from the address generation circuit in accordance with a rule required in FFT. Accordingly, the stored data is sequentially read from the designated memory cell row. The sequence of the data read is different from the sequence of the applied input data. That is, the sequence of the data read is in accordance with the sequence required in FFT.
In this way, it is pointed out that the amount of the operation to be processed by the CPU is increased in order to generate a write and a read address signals while the address generation circuit generates a write address signal and a read address signal. The CPU causes a write and a read address signals to be generated by operation in accordance with a program stored in the microprocessor. Such an operation is executed in a data arithmetic unit or an address arithmetic unit within the CPU. The amount of the operation processed by the microprocessor is increased, so that the operation speed of the microprocessor is reduced.